The present invention relates to a semiconductor device with a high breakdown voltage (which will be herein called a xe2x80x9chigh-voltage semiconductor devicexe2x80x9d).
Hereinafter, a known high-voltage semiconductor device will be described with reference to FIG. 14. FIG. 14 is a perspective view schematically illustrating a cross-sectional structure for an insulated-gate transistor.
As shown in FIG. 14, the transistor includes a p-type semiconductor substrate 1. In the substrate, n-type lightly doped semiconductor region 2, p-type doped isolating region 3, p-type doped body region 4 and n-type heavily doped source/drain regions 5 and 6 have been defined. These regions 2, 3, 4, 5 and 6 will be herein called xe2x80x9csemiconductor regionxe2x80x9d, xe2x80x9cisolating regionxe2x80x9d, xe2x80x9cbody regionxe2x80x9d and xe2x80x9csource/drain regionsxe2x80x9d, respectively, for the sake of simplicity. The isolating region 3 is provided to electrically isolate an adjacent pair of devices from each other. The body region 4 is defined in the semiconductor region 2, the source region 5 is defined in the body region 4 and the drain region 6 is defined in the semiconductor region 2.
An oxide film with non-uniform thicknesses has been deposited over the semiconductor region 2. A thinner portion of the oxide film is used as a gate oxide 7, while a thicker portion thereof is identified by the reference numeral 8. The oxide film 7, 8 is covered with an interlevel dielectric film 9. Electrodes 10b, 11b and 12b of polysilicon have also been formed over the oxide film 7, 8. Specifically, the electrode 10b functions as gate electrode, the electrode 11b is an electrically floating plate electrode, and the electrode 12b is a plate electrode connected to a drain electrode 15. It should be noted that parts of the interlevel dielectric film 9, which actually covers these electrodes 10b, 11b and 12b, are not illustrated in FIG. 14 to make the structure of this transistor easily understandable.
As also shown in FIG. 14, five other metal electrodes 13, 14, 15, 16 and 17 are also provided. Specifically, the electrode 13 is connected to the body region 4 and will be herein called a xe2x80x9cbody electrodesxe2x80x9d. The electrode 14 makes electrical contact with the source region 5 and will be herein called a xe2x80x9csource electrodexe2x80x9d. The electrodes 16 and 17 are electrically floating electrodes. And the electrode 15 makes electrical contact with the drain region 6 and will be herein called a xe2x80x9cdrain electrodexe2x80x9d. Although not illustrated in FIG. 14, a protective coating has actually been deposited over the electrodes 13 through 17 and interlevel dielectric film 9, and the chip including these components is entirely covered with a plastic encapsulant.
In the structure illustrated in FIG. 14, a predetermined part of the n-type semiconductor region 2 is surrounded with the p-type isolating region 3 in the p-type semiconductor substrate 1. The drain region 6 is located approximately at the center of that part of the semiconductor region 2. Also, the p-type body region 4 has been defined along the isolating region 3, which defines the periphery of that part the semiconductor region 2. And the n-type source region 5 has been defined inside the body region 4.
In the insulated-gate transistor shown in FIG. 14, a ground potential GND is applied to the source electrode 14, body electrode 13, substrate 1 and isolating region 3, a positive high potential is applied to the drain electrode 15 and a control voltage is applied to the gate electrode 10b. The plate electrodes 11b and 12b, connected to the drain region 6, are a type of field plates. These plate electrodes 12b and 11b are capacitively coupled to the floating metal electrodes 16 and 17, respectively, through the interlevel dielectric film 9 over the electrodes 12b and 11b. In this manner, the potential difference between the drain and gate electrodes 15 and 10b is divided by the capacitive divider so that potential is not concentrated at a particular surface area in the semiconductor region 2.
Next, it will be briefly described how the insulated-gate transistor shown in FIG. 14 operates. When a positive voltage, equal to or higher than its threshold voltage, is applied as a control voltage to the gate electrode 10b, part of the p-type body region 4, located near the surface and under the gate electrode 10b, changes into the opposite type, or n-type. As a result, a so-called xe2x80x9cchannel regionxe2x80x9d is created to turn the insulated-gate transistor ON. In this case, a current flows from the drain region 6 toward the source region 5 by way of the semiconductor region 2 and channel region near the surface of the body region 4. Conversely, if the voltage applied to the gate electrode 10b is reduced to less than its threshold voltage, then the channel region shrinks its size considerably to turn the insulated-gate transistor OFF. As used herein, the xe2x80x9cbreakdown voltagexe2x80x9d of a transistor means a voltage below which the transistor is kept OFF. Thus, a xe2x80x9chigh-voltage transistorxe2x80x9d can be kept OFF even when a high bias voltage (e.g., 100 V or more) is applied thereto.
FIG. 15 illustrates parasitic capacitances formed in the high-voltage semiconductor device shown in FIG. 14. FIG. 16 illustrates potential profiles created when a high voltage (e.g., 600 V) is applied to the device shown in FIG. 14. In FIG. 16, each dashed line indicates an equipotential line.
As shown in FIG. 15, a parasitic capacitance C1 exists between the gate and floating metal electrodes 10b and 17. A parasitic capacitance C2 exists between the floating metal and plate electrodes 17 and 11b. A parasitic capacitance C3 exists between the plate and floating metal electrodes 11b and 16. And a parasitic capacitance C4 exists between the floating metal electrode 16 and plate electrode 12b connected to the drain potential. A serial circuit, formed by these parasitic capacitances C1 through C4, divides the potential difference, thereby regulating the potential at the plate electrode 11b and creating appropriate potential profiles in the semiconductor region 2. It should be noted that parasitic capacitances C5 and C6, formed between the metal electrodes 16 and 17 and plastic encapsulant 19 shown in FIG. 15, are normally considered non-existent as will be described later.
Referring to FIG. 16, potential profiles at room temperature in the known high-voltage semiconductor device are schematically illustrated. The present inventors confirmed that the potential profiles illustrated in FIG. 16 and results of simulations we carried out showed similar tendencies.
The profiles illustrated in FIG. 16 were obtained where a ground potential of 0 V was applied to the substrate 1, isolating region 3, body region 4, source region 5 and gate electrode 10a and a voltage of 600 V was applied to the drain region 6. The control voltage applied to the gate electrode 10b was actually around 10 V. However, since this value is much lower than 600 V applied to the drain electrode 15, the same profiles are obtained whether the control voltage is 0 V or 10 V. Thus, the control voltage is regarded as 0 V for convenience sake.
As shown in FIG. 16, when the same high potential as that applied to the drain region 6, i.e., 600 V, is applied to the plate electrode 12b, an intermediate potential between 600 V and 0 V will be applied to the plate electrode 11b. Accordingly, the equipotential lines, representing the potential profiles in the semiconductor region 2, extend almost vertically to the surface of the semiconductor region 2, and are distributed almost equidistantly from each other. As a result, the concentration of electric field in the semiconductor region 2 can be reduced and the breakdown voltage of the transistor can be kept sufficiently high.
However, if the device is operated at an elevated ambient temperature of 150xc2x0 C. with a high voltage of 500 V or more (e.g., 600 V) continuously applied to the drain electrode 15, then the source-drain breakdown voltage (i.e., a breakdown voltage between the source and drain electrodes 14 And 15) decreases. This phenomenon can be simulated by a life test called a xe2x80x9chigh-temperature bias testxe2x80x9d. Generally speaking, as the voltage applied to the drain electrode 15 is increased, the decrease in breakdown voltage becomes more and more significant. Conversely, the lower the applied voltage, the less significant the decrease in breakdown voltage.
It is not yet completely clear how and why the source-drain breakdown voltage decreases during the high-temperature bias test. Thus, we have to infer the mechanism of the breakdown voltage decrease. Following is the conclusion of our inference.
In general, a semiconductor chip is packaged with a plastic encapsulant to prevent water or moisture from entering the plastic package. However, a novolac epoxy resin, a typical plastic encapsulant, contains 0.9% to 1.6% of hydroxyl (OH) groups. At an elevated temperature, these OH groups are activated and the plastic encapsulant 19, which is usually considered an insulator, becomes semi-insulating (i.e. electrically conductive at a high resistance).
In a high-voltage semiconductor device, a semiconductor chip is normally packaged with the plastic encapsulant 19 and multiple pads (not shown) on the chip are usually electrically connected to multiple external terminals (not shown, either) via metal fine wires (not shown, either). The ground potential of 0 V, supply voltage of 600 V and control signal are applied to those metal fine wires. Accordingly, when the plastic encapsulant 19 becomes semi-insulating through the above action of the activated OH groups, an intermediate potential between 600 V and 0 V is estimatingly applied to the surface of the protective coating 18. The intermediate potential is variable depending on the layout of the semiconductor chip in question. For example, where a ground pad (not shown) is located near the insulated-gate transistor on the chip and a power supply pad (not shown) is distant from the ground pad, part of the plastic encapsulant 19 over the insulated-gate transistor might be at an intermediate potential of about 100 V. In view of these respects, we estimated potential profiles that would be created if the interface between the protective coating 18 for the chip and the plastic encapsulant 19 had a potential of 100 V during the high-temperature bias test.
Hereinafter, the potential profiles at the time of the high-temperature bias test will be described with reference to FIG. 17. FIG. 17 illustrates the estimated potential profiles during the high-temperature bias test that was carried out at the same bias voltage as that applied for the room temperature profiles illustrated in FIG. 16. In FIG. 17, each dashed line indicates an equipotential line.
In FIG. 17, the floating metal electrode 17 is accompanied with not only the parasitic capacitances C1 and C2 but also with another parasitic capacitance C5 formed between the electrode 17 and plastic encapsulant 19 (see FIG. 15). In the same way, the other floating metal electrode 16 is accompanied with not only the parasitic capacitances C3 and C4 but also with another parasitic capacitance C6 formed between the electrode 16 and plastic encapsulant 19 (see FIG. 15). Accordingly, if the parasitic capacitance C5 or C6 has a value approximately equal to that of the sum of parasitic capacitances C1+C2 or C3+C4, then the plastic encapsulant 19 becomes semi-insulating during the high-temperature bias test. When a part of the plastic encapsulant 19 over the electrode 16 or 17 comes to have a potential of 100 V, the potential of the electrode 16, which was about 450 V at room temperature, decreases to about 300 V as being affected by the parasitic capacitance C6. In the same way, the potential of the electrode 17, which was about 150 V at room temperature, decreases to about 130 V as being affected by the parasitic capacitance C5. The potential at the plate electrode 11b, which was about 300 V at room temperature, also decreases to 200 V correspondingly. As a result, some of the equipotential lines, which cross the interface between the semiconductor region 2 and oxide film 8 and represent respective potentials of 200 V or more, bend toward the drain region 6 as shown in FIG. 17. And around the interface, the potential in the oxide film 8 becomes negative against the surface potential of the n-type semiconductor region 2.
Where part of the oxide film 8, located over the interface between the n-type semiconductor region 2 and oxide film 8, comes to have a negative potential in a high-temperature environment, Sixe2x80x94H bonds, Sixe2x80x94OH bonds and other bonds are broken in the interface, thus creating positive fixed charges. As for this phenomenon, see xe2x80x9cReliability Technology for Semiconductor Devicesxe2x80x9d published by Publisher of Japanese Union of Scientists and Engineers, for example. When the positive fixed charges are generated in the interface between the semiconductor region 2 and oxide film 8 by such a phenomenon, negative mobile charges are also created in the oxide film 8. The negative mobile charges in the oxide film 8 are attracted little by little to a positive high potential at the drain electrode 8 with time. As a result, the negative mobile charge density locally increases in a region of the oxide film 8 near the drain electrode 15, while the positive fixed charge density increases in the region where the negative mobile charges were originally created. A great number of negative charges exist in that region of the oxide film 8 over the interface and near the drain electrode 15. As a result, holes are attracted from the semiconductor region 2 toward that region, and the surface of the n-type semiconductor region 2 changes into the opposite type, or p-type, thus forming a p-type inversion layer 30. On the other hand, electrons are attracted from the semiconductor region 2 toward the region where the positive fixed charges remain, and the electron density locally increases in part of the semiconductor region 2 under the region with a high fixed charge density. As a result, an n-type accumulation layer 31 is formed near the surface of the semiconductor region 2.
Where the p-type inversion layer 30 and n-type accumulation layer 31 are formed in this way near the surface of the semiconductor region 2 as shown in FIG. 17, the electric field is locally concentrated at part of the p-type inversion layer 30 near the drain region 6. As a result, we believe, the breakdown voltage of the high-voltage semiconductor device decreases with time through such a mechanism.
Next, another known high-voltage semiconductor device will be described as a second prior art example with reference to FIG. 18. FIG. 18 illustrates a cross-sectional structure for a main part of a device according to the second prior art example. In FIG. 18, the same members as those of the first prior art example shown in FIG. 15 are identified by the same reference numerals and the description thereof will be omitted herein.
The device shown in FIG. 18 further includes p-type girdling regions 23 and 24 to have its breakdown voltage increased. Unlike the device of the first prior art example shown in FIG. 15, the device of the second prior art example does not have the floating metal electrodes 16 and 17 but includes the p-type girdling regions 23 and 24 in the n-type semiconductor region 2.
In the known device shown in FIG. 18, a parasitic capacitance C7 exists between the gate electrode 10b and girdling region 23. A parasitic capacitance C8 exists between the girdling region 23 and plate electrode 11b. A parasitic capacitance C9 exists between the plate electrode 11b and girdling region 24. And a parasitic capacitance C10 exists between the girdling region 24 and plate electrode 12b. A voltage applied between the drain and source electrodes 15 and 14 is divided by a serial circuit consisting of these parasitic capacitances C7 through C10, thereby defining potentials for the girdling regions 23 and 24 and plate electrode 11b. The potentials are determined probably this way at least at room temperature.
When the device with this structure is subjected to a high-temperature bias test as in the first prior art example, the plastic encapsulant 19 becomes semi-insulating. As a result, the surface of the protective coating 18 comes to have an intermediate potential between 600 V and 0 V. However, if the intermediate potential has decreased to 100 V, then the potential at the plate electrode 11b, which is about 300 V at room temperature, might decrease to about 200 V due to the existence of a parasitic capacitance C11 between the plastic encapsulant 19 and plate electrode 11b. In that case, the p-type inversion layer 30 is formed between the girdling regions 23 and 24 and these regions 23 and 24 become electrically conductive with each other. As a result, the breakdown voltage of the high-voltage semiconductor device adversely decreases.
It is therefore an object of the present invention to provide a highly reliable high-voltage semiconductor device, of which the source-drain breakdown voltage hardly decreases even when the device is operated at an elevated temperature.
An inventive high-voltage semiconductor device includes: semiconductor substrate of a first conductivity type; semiconductor region of a second conductivity type; source and drain regions of the second conductivity type; body region of the first conductivity type; gate insulating film; gate electrode; field insulating film; metal electrode; plate electrodes; and interlevel dielectric film. The semiconductor region is defined in the substrate. The drain region is defined approximately at the center of the semiconductor region. The body region is defined in the semiconductor region so as to be spaced apart from, and to surround, the drain region. The source region is defined in the body region. The gate insulating film is deposited over the body region. The gate electrode is formed on the gate insulating film. The field insulating film is deposited over a part of the semiconductor region between the body and drain regions. The metal electrode is electrically connected to the drain region. The plate electrodes are in an electrically floating plate state, and are spaced apart from, and surround, the drain region when the device is viewed from over the substrate. And the interlevel dielectric film is formed over the gate insulating film, the field insulating film and the plate electrodes. This device is characterized in that parts of the metal electrode are extended onto the interlevel dielectric film and located over the respective plate electrodes and that each said part of the metal electrode is capacitively coupled to an associated one of the plate electrodes.
In one embodiment of the present invention, when the device is viewed from over the substrate, the drain region may be approximately circular, while the body and source regions may be in the shape of rings that form concentric circles around the drain region.
In another embodiment of the present invention when the device is viewed from over the substrate, the drain region may be approximately circular, while the plate electrodes may be in the shape of rings that form concentric circles around the drain region. And the metal electrode may include, as the extended parts, a plurality of annular metal electrodes that are formed over the respective plate electrodes with the interlevel dielectric film interposed therebetween. Each said annular metal electrode may be electrically connected to the drain region.
In this particular embodiment, at least one of the annular metal electrodes may be smaller in width than an associated one of the plate electrodes that is capacitively coupled to the annular metal electrode.
Alternatively, the metal electrode may include a part that overlaps the entire upper surface of one of the plate electrodes, which is located closer to the drain region than any other one of the plate electrodes is, with the interlevel dielectric film interposed therebetween.
As another alternative, the more distant from the drain region each said annular metal electrode is, the smaller the width of the annular metal electrode may be.
In still another embodiment, a plurality of girdling regions of the first conductivity type may be defined in respective upper parts of the semiconductor region that are located under the plate electrodes.
In yet another embodiment, a plurality of girdling regions of the first conductivity type, which are in the shape of rings that form concentric circles around the drain region, may be defined in respective upper parts of the semiconductor region that are located under the plate electrodes.
In yet another embodiment, the device may further include an isolating region of the first conductivity type that surrounds the semiconductor region. And the semiconductor region may be electrically isolated using a junction formed between the semiconductor and isolating regions.
In an alternative embodiment, the device may further include an isolating insulating film that surrounds the semiconductor region. And the semiconductor region may be electrically isolated using the insulating film.
In still another embodiment, the device may further include an insulating layer formed on the substrate of the first conductivity type. And the semiconductor region of the second conductivity type may be defined on the insulating layer.
In yet another embodiment, the device may further include: a protective coating formed over the metal electrode and the interlevel dielectric film; and a plastic encapsulant formed on the protective coating.